// IVB checksum: 44700525
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File name   :  vv_ahblite_system_smp.e
Title       :  System Signal Map unit
Project     :  vv_ahblite UVC
Developers  :  stefan, filip
Created     :  26.07.2011.
Description :  This file implements the system signal map of the UVC.

Notes       :  The system smp is a unit that contains external ports
    :  for HW signals that are common to the whole design, and related events.
    :  Typically, this includes clock and reset signals and events.
    :  The bus monitor unit and all agent units have references to
    :  those events, this makes the units independent.
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Copyright  (c)2011
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<'
package vv_ahblite;

-- ==========================================================================
-- Synchronizer unit for the environment. Contains the clock and other
-- synchronizing events.Enables agents instantiation independent of
-- vv_ahblite_env
-- ==========================================================================
unit vv_ahblite_system_smp {
    
    -- This field is the logical name of the env associated with this
    -- synchronizer. This field is automatically constrained by the UVC. Do
    -- constrain it manually.
    env_name   : vv_ahblite_env_name_t;
    
    -- Current cycle number 
    current_cycle   : uint;
        keep current_cycle == 0;
    
    -- Global Signals
    clk        : inout simple_port of bit is instance;
    resetn       : inout simple_port of bit is instance;
    --primary reset for all bus elements, active value is LOW in AHB-lite protocol
    
    -- This field is used to keep track of the current reset state.
    -- By default, reset is assumed to be asserted at the start of the test.
    -- The user should not normally need to constrain this field.
    !reset_asserted : bool;
    
    -- This field is used to constraint the UVCs reset polarity
    is_active_high : bool;
        keep soft is_active_high == FALSE;
    
    -- This event gets emitted each time the reset signal changes state. Note
    -- that, depending on how reset is generated, it is possible that this
    -- event will be emitted at time zero.
    event reset_change is change(resetn$) @sim;
    
    -- This event gets emitted when reset is asserted.
    event reset_start;
    
    -- This event gets emitted when reset is de-asserted.
    event reset_end;
    
    on reset_change {
        if resetn$ == is_active_high.as_a(bit) {
            reset_asserted = TRUE;
            emit reset_start;
    } else {
            reset_asserted = FALSE;
            emit reset_end;
        };
    };
    
    -- This event is the rising edge of the clock, unqualified by reset.
    event unqualified_clk is rise(clk$) @sim;
    
    -- This event is the rising edge of the clock, qualified by reset.
    event clk;
    on unqualified_clk {
        current_cycle += 1;
        if (not reset_asserted) {
            emit clk;
        };
    };
    
    post_generate() is also {
        reset_asserted = is_active_high.as_a(bit) == resetn$;
    };
   
};

'>
